Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA
| Autor: | D. A. Zheleznikov, V.M. Khvatov |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Computer science Design flow CAD 02 engineering and technology Integrated circuit 021001 nanoscience & nanotechnology 01 natural sciences law.invention Computer architecture law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Routing (electronic design automation) Physical design 0210 nano-technology Cluster analysis Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN Block (data storage) |
| Zdroj: | 2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus). |
| DOI: | 10.1109/elconrus51938.2021.9396219 |
| Popis: | IP-core is a block with a complex function that can be re-used in integrated circuits design. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA it is necessary to develop IP-cores libraries that allow identifying blocks on every stage of flow.This article shows IP-core libraries types and forms used as a part of design flow developed by IPPM RAS for Russian FPGA. It describes challenges of libraries for logical synthesis development and automatic mapping on an existing basis. The paper presents libraries needed by CAD on every stage of physical design for clustering, placement and routing. Also, it considers soft and hard IP-cores libraries distinct features and methods of their formation taking into account the FPGA architecture. |
| Databáze: | OpenAIRE |
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