Dynamic in-chip current distribution simulation technology for power device layout design

Autor:	N. Nagata, B. Shi, K. koba, S. Hojo, T. Saito, T. Chiba, H. Shimizu
Rok vydání:	2021
Předmět:	Page layout Computer science Spice Hardware_PERFORMANCEANDRELIABILITY Integrated circuit computer.software_genre Chip Power (physics) law.invention law Hardware_INTEGRATEDCIRCUITS Electronic engineering Power semiconductor device Parasitic extraction Design methods computer
Zdroj:	2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Popis:	This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice model, and layout parasitic extraction technology for power devices and linking them seamlessly. We report that this method was applied to the layout optimization of our 8th generation IGBTs, and the in-chip current variation could be reduced by about 50% compared to the conventional layout structure.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::bc5883fe0a1a12eff9ac9c588b405345 https://doi.org/10.23919/ispsd50666.2021.9452233 Zobrazit plný text záznamu