An IEC 61131-3-based PLC implemented by means of an FPGA

Autor: Józef Kulisz, Robert Czerwinski, Miroslaw Chmiel, A. Krzyzyk, M. Rosol, P. Smolarek
Rok vydání: 2016
Předmět:
0209 industrial biotechnology
Floating point
Comparator
Computer Networks and Communications
Computer science
IEC 61131-3
02 engineering and technology
Programmable logic array
Instruction set
Arithmetic logic unit
020901 industrial engineering & automation
Application-specific integrated circuit
Artificial Intelligence
0202 electrical engineering
electronic engineering
information engineering
Saturation arithmetic
Hardware_ARITHMETICANDLOGICSTRUCTURES
Erasable programmable logic device
Field-programmable gate array
Simple programmable logic device
Register-transfer level
computer.programming_language
Hardware architecture
business.industry
020208 electrical & electronic engineering
Programmable logic controller
Instruction list
Macrocell array
Programmable logic device
Programmable Array Logic
Logic synthesis
Hardware and Architecture
Embedded system
Central processing unit
business
computer
Software
Zdroj: Microprocessors and Microsystems. 44:28-37
ISSN: 0141-9331
Popis: The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of instruction list and hardware architecture design are presented, however two aspects are the most important: Central Processing Unit (CPU) and the Arithmetic and Logic Unit (ALU). The ALU can execute 34 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The developed PLC is implemented using an FPGA device; however, the HDL models used for synthesis can be easily ported to an ASIC.
Databáze: OpenAIRE
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