| Popis: |
A process-, voltage-, and temperature-(PVT) insensitive low-voltage tracking RC compensation scheme is described which cancels the pole due to the load capacitance using a Miller zero generated by the frequency compensation network. A low-voltage constant current source with no back-gate effect (a "k’ generator") is used to generate the bias currents for the OTA. The architecture, implemented in a TSMC 180nm CMOS process, achieves a 2X power reduction compared to a widely-used active-RC compensation scheme. Small-signal settling times are compared across process corners for both approaches. The low- voltage approach is shown to be more robust than the latter which suffers from slower settling due to the formation of doublets. |
