A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
| Autor: | V. Chikarmane, M. Hattendorf, S. Kosaraju, Abdur Rahman, M. Sprinkle, A. Tura, V. Sharma, G. Leatherman, H. Gomez, G. Ding, D. Towner, P. Sinha, C. Auth, S. Jaloviar, J. Birdsall, I. Post, B. Ho, D. Bergstrom, J. Leib, K. Lee, T. Mule, D. Hanken, M. Asoro, A. Saha, M. Sharma, C. Pelto, H. Meyer, M. Prince, L. Pipes, C. Staus, J. Shin, R. Heussner, S. Parthasarathy, C. Parker, V. Bhagwat, C. Ward, J. Dacuna Santos, M. Buehler, H. Hiramatsu, R. Suri, A. Aliyarukunju, M. Haran, S. Rajamani, A. Tripathi, P. Smith, A. Madhavan, W. Han, A. Yeoh, N. Bisnik, K. Marla, S. Joshi, H. Kothari, Q. Fu, I. Jin, S. Kirby, A. St. Amour |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Interconnection Materials science business.industry Transistor Strained silicon 02 engineering and technology Dielectric 021001 nanoscience & nanotechnology 01 natural sciences law.invention Stack (abstract data type) CMOS law Logic gate 0103 physical sciences Optoelectronics 0210 nano-technology business Metal gate |
| Zdroj: | 2017 IEEE International Electron Devices Meeting (IEDM). |
| DOI: | 10.1109/iedm.2017.8268472 |
| Popis: | A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology. |
| Databáze: | OpenAIRE |
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