Semiclassical and wave mechanical modeling of charge control and direct tunneling leakage in MOS and H-MOS devices with ultra-thin oxides
| Autor: | Eric Cassan, P. Dollfus, P. Hesto, S. Galdin |
|---|---|
| Rok vydání: | 2001 |
| Předmět: |
Materials science
Condensed matter physics Semiconductor device modeling Hardware_PERFORMANCEANDRELIABILITY Electronic Optical and Magnetic Materials Threshold voltage CMOS Charge control Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Poisson's equation Quantum tunnelling AND gate Hardware_LOGICDESIGN Leakage (electronics) |
| Zdroj: | IEEE Transactions on Electron Devices. 48:715-721 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/16.915702 |
| Popis: | Charge control and gate leakage in metal-oxide-semiconductor (MOS) structures and heterojunction-MOS structures with ultrathin oxide (1 nm) are investigated using both classical and wave-mechanical calculations. In the classical approach, direct tunneling gate current is determined using the formalism of transmission probability whereas the notion of quasibound state lifetime is applied in the wave mechanical model. For conventional MOS structure, the threshold voltage V/sub T/ significantly depends on the applied model but an excellent agreement between both approaches is found about gate leakage provided that the correction of V/sub T/ is taken into account. For buried-channel H-MOS structures the quantum-induced V/sub T/-shift is smaller but the degradation of gate control efficiency dn/sub s//dV/sub g/ is increased, due to a large charge displacement from the oxide interface resulting from 2-D confinement in the buried strained layer. Using semiclassical approach the error of inversion charge distribution yields an overestimation of gate leakage compared with the more rigorous wave-mechanical calculation. It is finally shown by properly solving self-consistently Poisson and Schrodinger equations that a heterojunction-channel architecture may reduce the gate leakage by at least two orders of magnitude compared with conventional MOS design. This improvement would be in addition to the expected increase of device performance due to the strain-induced enhancement of electron transport properties. |
| Databáze: | OpenAIRE |
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