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This study presents a comparative study of single, regular and flip well subthreshold SRAMs in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port has been used as a case study. Simulation results, based on the extracted netlist from layout, show that the speed of the flip well SRAM is significantly better than that of the single and regular well SRAMs. In terms of leakage current, single well is the best option. The regular well type has lower static noise margin (SNM) variability. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as driver transistors and RVT for the rest of the transistors. This study may help designers to select an optimal architecture based on their application and performance requirements. The 22 nm FDSOI technology enables a wide range of back gate bias voltages to improve the read stability and write ability of the SRAMs and, hence, their minimum operating voltage and power consumption. |
