Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique
| Autor: | Hong-Yeh Chang, Yen-Liang Yeh, Shu-Yan Huang, Chun-Ching Chan, Ian Yi-En Shen |
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| Rok vydání: | 2016 |
| Předmět: |
Radiation
Materials science 020208 electrical & electronic engineering dBc 020206 networking & telecommunications 02 engineering and technology Condensed Matter Physics Phase-locked loop Voltage-controlled oscillator CMOS Robustness (computer science) Phase noise 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Voltage Jitter |
| Zdroj: | IEEE Transactions on Microwave Theory and Techniques. 64:4632-4645 |
| ISSN: | 1557-9670 0018-9480 |
| DOI: | 10.1109/tmtt.2016.2623784 |
| Popis: | Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed $K$ -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are −114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies. |
| Databáze: | OpenAIRE |
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