2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products
| Autor: | Milam Paraschou, Kevin M. Lepak, Samuel D. Naffziger, Mahesh Subramony |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Computer science
business.industry Bandwidth (signal processing) Process (computing) 020207 software engineering 02 engineering and technology Backward compatibility 020202 computer hardware & architecture Embedded system 0202 electrical engineering electronic engineering information engineering Key (cryptography) Static random-access memory Routing (electronic design automation) business Electronic circuit |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc19947.2020.9063103 |
| Popis: | AMO's “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targeting server and client markets, respectively (Fig. 2.2.1). The chiplet architecture enables leading edge 7nm [1] CPUs for multiple markets, while retaining backward compatibility to complex 10 and memory subsystems in a scalable design with high reuse for improved time-to-market. A key benefit is the heterogeneous technology deployed between the CPUs and the 10/mixed-signaIP. It is well known that shrink factors in advanced nodes are much lower for analog circuitry than for digital logic and SRAM. By keeping the memory interfaces and SerOes in mature 12nm technology, costs are mitigated since those circuits see a very small shrink factor to 7nm and very little performance or power gain from advanced nodes. A low-cost 12nm 10 die (IOD) with the high-yielding 8 “Zen2” core, 74mm2 7nm CPU compute die (CCD) combine to provide very cost-effective performance. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|