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This paper proposes new frequency-domain (FD) metrics to evaluate and optimize interconnects for high-speed IO. In this paper, we focused on a spring-probe socket for interconnects and PCIe Gen3 for the high-speed IO. For design optimization, we adapted a holistic approach utilizing response surface methodology. Using the proposed metrics, the spring-probe socket design was optimized to minimize impact on the IO channel performance. In order to check the validity of the new metrics, an optimized socket design via voltage margin and timing margin from eye opening was compared. |
