| Autor: |
Danny Pak-Chum Shum, Kyung Joon Han, R. Broze, Volker Hecht, A. Yang, R. Kakoschke, N. Chan, L. Pescini, Armin Tilke, Sung-Rae Kim, Martin Stiftinger |
| Rok vydání: |
2006 |
| Předmět: |
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| Zdroj: |
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.. |
| DOI: |
10.1109/iedm.2005.1609346 |
| Popis: |
A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A deep trench isolation (DTi) process module enables an isolated Pwell (IPW) bias scheme for the first time, leading to flash write/erase (W/E) by FN tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. The HV bias can be scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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