Designing and Benchmarking of Double-Row Height Standard Cells
| Autor: | Rung-Bin Lin, Cheng-Wei Tai, Shang-Rong Fang, Yu-Xiang Chiang, Jin-Kai Yang, Yuan-Dar Chung, Kai-Chun Peng |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Standard cell
Transistor Double row 02 engineering and technology Integrated circuit design Benchmarking Chip 01 natural sciences 020202 computer hardware & architecture Computational science law.invention 010309 optics law Chip-scale package 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Mathematics |
| Zdroj: | ISVLSI |
| DOI: | 10.1109/isvlsi.2018.00022 |
| Popis: | This article presents our experience of designing double-row height standard cell libraries and their use for chip designs. Seven cell libraries are designed based on the 15nm process technology stipulated in FreePDK15. A single-row height of 7.5 M2 tracks is used as a basis for designing double-row height cells. Two minimum-sized transistors, one having two fins and the other having four fins, are employed to design 1X drive-strength cells. Among the seven libraries, two libraries consist of only single-row height cells. The other five libraries each consist of partly single-row height cells and double-row height cells. Our experiments show that a double-row height library can achieve on average -2% to 21% area saving and -23% to 19% smaller power-delay-area product. Our results also show that using a large minimum-sized transistor for designing a double-row height library is not viable if extensive transistor folding is required. |
| Databáze: | OpenAIRE |
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