| Autor: |
Savithri Sundareswaran, Rajendran Panda, L. Nechanicka, R. Solovyev, S. Gavrilov, Jacob A. Abraham |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
SoCC |
| DOI: |
10.1109/socc.2008.4641543 |
| Popis: |
Timing margining is a key component of timing sign-off. Insufficient margin can lead to silicon failure and excessive pessimistic margin will entail unnecessary design optimization effort. Timing margin is intended to cover the uncertainty in clock arrival times and clock skews arising from within-die process variations. In highly scaled technologies, the increased process variations tend to enforce an overestimation of timing margins making it difficult for the designs to achieve the target performance. In this paper, we present a more efficient margining methodology to account for clock-skew variations arising due to within-die variations. The proposed methodology fits well within current corner based timing sign-off framework and allows for significant reduction in margin pessimism. We present the results and observations on a low power processor for hold-time margin correction. Evaluation of the proposed methodology for hold analysis on a low power processor shows, on average, ~67% reduction in the original margin. Further the margin correction decreases the number of hold-time violations significantly and effectively achieves 10times reduction in hold-violation fixing effort. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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