An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing
| Autor: | Azadeh Alsadat Emrani Zarandi, Yavar Safaei Mehrabani, Roghayeh Ataie |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Motion detector
Adder Computer science 020208 electrical & electronic engineering Transistor 020206 networking & telecommunications Image processing 02 engineering and technology law.invention law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Figure of merit Electrical and Electronic Engineering MATLAB computer Hardware_LOGICDESIGN computer.programming_language Block (data storage) Electronic circuit |
| Zdroj: | International Journal of Electronics. 106:928-944 |
| ISSN: | 1362-3060 0020-7217 |
| DOI: | 10.1080/00207217.2019.1576232 |
| Popis: | The design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, po... |
| Databáze: | OpenAIRE |
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