Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

Autor:	Merritt Funk, Qingyun Yang, Joyce C. Liu, Matthew Sendelbach, Jeffrey S. Brown, Daniel J. Prager, Peter E. Cottrell, David V. Horak, Eric P. Solecky, Randy W. Mann, Sadanand V. Deshpande, Wesley C. Natzle, F. Higuchi, Chienfan Yu, Hussein I. Hanafi, Akihisa Sekiguchi, Subramanian S. Iyer, W. Yan, Bruce B. Doris, Masayuki Tomoyasu, James P. Norum, Len Y. Tsou, Asao Yamashita, Hiroyuki Takahashi
Rok vydání:	2004
Předmět:	Materials science Silicon business.industry Oxide chemistry.chemical_element Nanotechnology Trim chemistry.chemical_compound chemistry Resist Etching (microfabrication) Logic gate Optoelectronics Reactive-ion etching business Lithography
Zdroj:	2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).
Popis:	A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ba080838e461856e140db41f0f32479a https://doi.org/10.1109/asmc.2004.1309536 Zobrazit plný text záznamu