| Autor: |
Yukiyasu Arisawa, Noriaki Oda, Kazuo Tawarayama, Ichiro Mori, Takashi Kamo, Daisuke Kawamura, Hiroyuki Tanaka, Kentaro Matsunaga, Yuusuke Tanaka, Toshihiko Tanaka, Hajime Aoyama, Taiga Uno, Naofumi Nakamura, Eiichi Soda, Shuichi Saito |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
SPIE Proceedings. |
| ISSN: |
0277-786X |
| Popis: |
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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