Performance comparison review of 8–3 compressor on FPGA
| Autor: | Patrick Sebastian, Yuhao Leong, Micheal Drieberg, Abu Bakar Sayuti, Hai Hiung Lo |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Adder
Power–delay product Computer science business.industry 020209 energy 02 engineering and technology Multiplexer Multiplexing Logic gate 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Gas compressor Computer hardware Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | TENCON 2017 - 2017 IEEE Region 10 Conference. |
| DOI: | 10.1109/tencon.2017.8228275 |
| Popis: | Compressors are commonly utilized in multipliers for reducing partial products in a parallel manner. In this paper 7–3, 7–4, 8–3, 8–4, 9–3, and 9–4 compressors designed with adder circuits or multiplexer circuits were implemented in Altera EP2C70F896 FPGA and their performance compared in terms of number of logic gates used, cell area and power delay product (PDP) for an optimum recommendation for the implementation of 8–3 compressor design in FPGA. |
| Databáze: | OpenAIRE |
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