Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
| Autor: | Daisuke Kosaka, Makoto Nagata, Tetsuro Matsuno |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Digital electronics
Sequential logic Pass transistor logic Computer science business.industry Applied Mathematics Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Logic level Computer Graphics and Computer-Aided Design Integrated injection logic CMOS Logic gate Signal Processing Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Pull-up resistor Hardware_LOGICDESIGN |
| Zdroj: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :440-447 |
| ISSN: | 1745-1337 0916-8508 |
| DOI: | 10.1587/transfun.e93.a.440 |
| Popis: | Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology. |
| Databáze: | OpenAIRE |
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