Continuous time sigma delta ADC design and non-idealities analysis
| Autor: | Chen Zhenhai, Yang Yintang, Yuan Jun, Wu Jun, Wang Chao, Zhang Zhaofeng, Qian Wenrong |
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| Rok vydání: | 2011 |
| Předmět: |
Physics
Comparator Amplifier Clock rate Condensed Matter Physics Delta-sigma modulation Electronic Optical and Magnetic Materials law.invention CMOS Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS Materials Chemistry Electronic engineering Operational amplifier Electrical and Electronic Engineering Jitter Electronic circuit |
| Zdroj: | Journal of Semiconductors. 32:125007 |
| ISSN: | 1674-4926 |
| Popis: | A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed non-idealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. Athird-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply. |
| Databáze: | OpenAIRE |
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