A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET
| Autor: | R.W. Young, M. Ieong, L. Su, S. Kapur |
|---|---|
| Rok vydání: | 1998 |
| Předmět: |
Materials science
Silicon Dopant business.industry Electrical engineering chemistry.chemical_element Polysilicon gate Capacitance Electronic Optical and Magnetic Materials Mechanism (engineering) chemistry CMOS MOSFET Optoelectronics Electrical and Electronic Engineering business Communication channel |
| Zdroj: | IEEE Electron Device Letters. 19:234-236 |
| ISSN: | 1558-0563 0741-3106 |
| DOI: | 10.1109/55.701427 |
| Popis: | A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO/sub 2/ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,. |
| Databáze: | OpenAIRE |
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