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This paper mainly described about design and synthesis of 16-bit Karatsuba multiplier using Square root carry select adder (SRCSA) circuit. The Carry look ahead adder (CLA), Carry save adder (CSA) and SRCSA are modelled using Verilog HDL. The functional verification of all the adders is carried out in Cadence NClaunch tool. All the adders are synthesized in Cadence Genus tool. The power, timings and area reports can be generated in the synthesis flow. The comparative analysis done between CLA, CSA and SRCSA. Later choose SRCSA for the multiplier. The Karatsuba multiplier is designed using the Verilog HDL. The functional verification of the multiplier circuit is carried using Verilog (RTL file) and test bench in NCLaunch tool from cadence. The synthesis of multiplier circuit is carried in Genus tool from Cadence, it converts the RTL file to gate-level netlist. During synthesis, reported the power is 193385.696 nW, Delay is 3409ps and area is 2795.508nm2. All process has been carried out using the 180nm technology. |
