DFT processor implementation scheme based on Rader algorithm
| Autor: | Benouaret Mohamed, Harize Saliha, Aouissi Samiha |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Virtex Signal processing business.industry Computer science 020208 electrical & electronic engineering Fast Fourier transform 02 engineering and technology 01 natural sciences Discrete Fourier transform Control and Systems Engineering 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Wireless Electrical and Electronic Engineering business Field-programmable gate array Algorithm Twiddle factor Data transmission |
| Zdroj: | IET Circuits, Devices & Systems. 13:385-390 |
| ISSN: | 1751-8598 1751-858X |
| DOI: | 10.1049/iet-cds.2018.5200 |
| Popis: | The implementation of a discrete Fourier transform (DFT) algorithm plays a key role in many real-time applications. This study mainly deals with the design and implementation of a DFT processor with non-power-of-two (prime) problem sizes using the Rader algorithm. The proposed design focuses on increasing the speed to fulfil the requirements of the real-time data transmission by enabling data rates up to 10 Gbps. Despite its limitation to the prime size, it remains a promising tool in the signal processing aspect and takes its place among other techniques to achieve high-speed wireless communication. By avoiding the cumbersome process during twiddle factors computation as well as the butterfly structure, the outcome preludes to an ambitious architecture dedicated to high-speed design reaching over 233 and 92 MHz for DFT lengths of 7 and 67, respectively, on Virtex 6. Thereby, the obtained results prove the efficiency of the algorithm and show the trade-off to be established in terms of occupied area, throughput, latency, and power consumption. |
| Databáze: | OpenAIRE |
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