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The market trend of secure products is to offer more users' services and security. Thus, electronic devices must be flexible and reconfigurable in the way they permit executing further algorithms than those designed for. In this paper, in order to encrypt/decrypt data blocks, a Reconfigurable Cryptography Coprocessor (RCC) for Advanced Encryption Standard (AES/Rijndael) is developed. The AES offers a good combination of security, performance, efficiency, implementability and flexibility. We propose a RCC by using a Systolic Processor (SP) based on: i) Processing Element (PE) array, and ii) Controller with a Finite State Machine (FSM) and a memory. The advantages are: i) provide a solution to compute all matrix format data and ii) the PE array's data path is reconfigurable via the FSM. Finally, the conception and implementation were carried out by using Very High Speed Integrated Circuit Hardware Description (VHDL) language and Xilinx ISE 7.1 simulator. |
