Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression
| Autor: | S. H. Mozafari, Jonah Caplan, Brett H. Meyer, Maria Isabel Mera, Peter Milder |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
business.industry Computer science Data_CODINGANDINFORMATIONTHEORY 02 engineering and technology 01 natural sciences Fletcher's checksum 020202 computer hardware & architecture Life-critical system Application-specific integrated circuit Hardware and Architecture Embedded system Cyclic redundancy check 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) business Field-programmable gate array Implementation Software Data compression |
| Zdroj: | ACM Transactions on Embedded Computing Systems. 16:1-20 |
| ISSN: | 1558-3465 1539-9087 |
| DOI: | 10.1145/3063312 |
| Popis: | An emerging trend in safety-critical computer system design is the use of compression—for example, using cyclic redundancy check (CRC) or Fletcher checksum (FC)—to reduce the state that must be compared to verify correct redundant execution. We examine the costs and performance of CRC and FC as compression algorithms when implemented in hardware for embedded safety-critical systems. To do so, we have developed parameterizable hardware-generation tools targeting CRC and two novel FC implementations. We evaluate the resulting designs implemented for FPGA and ASIC and analyze their efficiency. While CRC is often best, FC dominates when high throughput is needed. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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