| Autor: |
J.-H. Park, J. Lee, J. Jeong, U. Pi, W.K. Kim, S. Lee, E. Noh, K. Kim, W. C. Lim, S. Kwon, B.-J. Bae, I. Kim, N. Ji, K. Lee, H. Shin, S. H. Han, S. Hwang, D. Jeong, S. C. Oh, S. O. Park, Y. J. Song, G. T. Jeong, G. H. Koh, S. Hyun, K. Hwang, S. W. Nam, H. K. Kang, E. S. Jung |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
2019 IEEE International Electron Devices Meeting (IEDM). |
| DOI: |
10.1109/iedm19573.2019.8993614 |
| Popis: |
We demonstrate a novel way of integrating STT-MRAM for on-chip hybrid memory which exhibits either features of high-retention or high-speed implemented in separate zones in a single chip. For satisfying high-temperature retention requirement, tailored MTJs are shown to support > 10 year retention at 220°C. For high-speed operation, critical improvements have been made in terms of TMR, short fail probability, overdrive and write error rate. The new integration provides a manufacturable way of combining diverse memory components by modulating non-volatility of STT-MRAM without affecting within-chip distributions of critical properties. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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