Short-channel epitaxial germanium pMOS transistors
| Autor: | Roger Loo, K. De Meyer, Geert Eneman, B. De Jaeger, Eddy Simoen, David P. Brunco, Geert Hellings, Marc Meuris, Gang Wang, Matty Caymax, Jerome Mitard, C. Claeys, M.M. Heyns |
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| Rok vydání: | 2010 |
| Předmět: |
Thin layers
Materials science business.industry Gate dielectric Transistor Metals and Alloys Nanotechnology Equivalent oxide thickness Surfaces and Interfaces Surfaces Coatings and Films Electronic Optical and Magnetic Materials PMOS logic law.invention law Shallow trench isolation Materials Chemistry Optoelectronics Wafer business Leakage (electronics) |
| Zdroj: | Thin Solid Films. 518:S88-S91 |
| ISSN: | 0040-6090 |
| Popis: | This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1 V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5. Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 °C) recipe with a Si3H8 precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below. Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control. |
| Databáze: | OpenAIRE |
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