First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Autor: Jerome Mitard, Frank Holsteyns, Andriy Hikavyy, A. Opdebeeck, Alexey Milenin, Hugo Bender, Dan Mocuta, E. Capogreco, Hiroaki Arimura, Roger Loo, Geert Eneman, Kathy Barla, Farid Sebaai, Niamh Waldron, Kurt Wostyn, E. Dentoni Litta, Clement Porret, Nadine Collaert, Robert Langer, Liesbeth Witters, Andreas Schulze, V. De Heyn, Paola Favia, Christa Vrancken
Rok vydání: 2018
Předmět:
Zdroj: IEEE Transactions on Electron Devices. 65:5145-5150
ISSN: 1557-9646
0018-9383
Popis: This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.
Databáze: OpenAIRE