A many-core architecture for in-memory data processing
| Autor: | Arun Raghavan, Cagri Balkesen, Venkatraman Govindaraju, Georgios Giannikis, Venkatanathan Varadarajan, Eric Sedlar, Charlie Roth, Nipun Agarwal, Evangelos Vlachos, Sam Idicula, Sandeep R. Agrawal |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Xeon business.industry Computer science Processor design 02 engineering and technology 01 natural sciences Memory controller 020202 computer hardware & architecture Microarchitecture Data processing system Shared memory Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Hardware acceleration business Computer hardware Performance per watt |
| Zdroj: | MICRO |
| DOI: | 10.1145/3123939.3123985 |
| Popis: | For many years, the highest energy cost in processing has been data movement rather than computation, and energy is the limiting factor in processor design [21]. As the data needed for a single application grows to exabytes [56], there is clearly an opportunity to design a bandwidth-optimized architecture for big data computation by specializing hardware for data movement. We present the Data Processing Unit or DPU, a shared memory many-core that is specifically designed for high bandwidth analytics workloads. The DPU contains a unique Data Movement System (DMS), which provides hardware acceleration for data movement and partitioning operations at the memory controller that is sufficient to keep up with DDR bandwidth. The DPU also provides acceleration for core to core communication via a unique hardware RPC mechanism called the Atomic Transaction Engine. Comparison of a DPU chip fabricated in 40nm with a Xeon processor on a variety of data processing applications shows a 3× - 15× performance per watt advantage.CCS CONCEPTS• Computer systems organization $\rightarrow$ Multicore architectures; Special purpose systems |
| Databáze: | OpenAIRE |
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