| Popis: |
Compared with their digital counterparts, LDPC analog decoders own higher power efficiency which is suitable for low-power-consumptions applications. However, the high designing complexity of analog decoders with long block length has impeded their real-world applications. This paper presents a method to construct LDPC codes that can lower the designing complexity significantly by using identical models to form the whole decoder, as well as rules that codes should satisfy. Simulation results show that the proposed LDPC codes could lower the designing complexity with little performance lose and have better error-correcting performance than codes in CCSDS standard. |
