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A citric buffer etch has been developed and used to create an optimized etch-stop process for the manufacture of recessed gate GaAs/AlGaAs FETs. Selectives in excess of 1800 have been achieved for a 25 /spl Aring/, x=0.35 Al/sub x/Ga/sub 1-x/As stop layer with the advantage of no iron damage to the channel. Stop layer thicknesses from 15 /spl Aring/ to 100 /spl Aring/ and Al content from x=0.25 to x=0/5 were investigated for process robustness and FET performance. The high selectivity permits the use of a thin 25 /spl Aring/ stop layer of x=0.35 material that does not perturb FET performance, and still provides a robust process. Performance is verified with DC and RF tests, including small signal extrinsic transconductance, and FET noise figure, which are particularly sensitive to increased source resistance. With the etch-stop process, uniformity is greatly enhanced. The standard deviation for Idss was reduced from 20%-30% to less than 5%, and standard deviation for threshold voltage was reduced from 300 mV to less than 30 mV. This proces is applicable to a wide variety of heterostructure devices. > |
