A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device
| Autor: | Sang-Hun Seo, Kyeong-Tae Kim, Kwang-Ok Koh, Moo-sung Kim, Won-suk Yang, Han-sin Lee, Seung-Hyun Park |
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| Rok vydání: | 2002 |
| Předmět: |
Materials science
business.industry Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Electronic Optical and Magnetic Materials PMOS logic law.invention Ion implantation CMOS law Low-power electronics MOSFET Hardware_INTEGRATEDCIRCUITS Optoelectronics Static random-access memory Electrical and Electronic Engineering business Hardware_LOGICDESIGN Leakage (electronics) |
| Zdroj: | IEEE Electron Device Letters. 23:719-721 |
| ISSN: | 1558-0563 0741-3106 |
| Popis: | A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology. |
| Databáze: | OpenAIRE |
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