A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

Autor: S.Y. Chang, Hon-Jarn Lin, S.H. Yang, R. Chen, R.F. Tsui, Jhon-Jhy Liaw, S. M. Jang, M.C. Chiang, C. H. Hsieh, C.H. Yao, P N Chen, K T Lai, Y S Mor, Lin Chih-Yung, Chun-Kuang Chen, Kuang-Hsin Chen, Chia-Pin Lin, J.H. Chen, C.H. Tsai, Y. Ku, T. Miyashita, Ming-Huan Tsai, C. H. Lee, Chang Chih-Yang, Hou-Yu Chen, K.H. Pan, Shien-Yang Wu, Joy Cheng, C S Liang, Kuei-Shun Chen, C.H. Chang, Vincent S. Chang
Rok vydání: 2016
Předmět:
Zdroj: 2016 IEEE International Electron Devices Meeting (IEDM).
DOI: 10.1109/iedm.2016.7838333
Popis: For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.
Databáze: OpenAIRE