| Autor: |
U. Langmann, E. Schlag, D. Clawin, Z.H. Lao, J.N. Albers |
| Rok vydání: |
1995 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 30:129-132 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.341739 |
| Popis: |
The 4:1-multiplexer reported here is based on a 21 GHz f/sub T/ 0.4 /spl mu/m silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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