IBM z14™: 14nm microprocessor for the next-generation mainframe
| Autor: | Jose L. Neves, Ofer Geva, Anthony Saporito, Mark Cichanowski, Christopher J. Berry, Christian Jacobi, John Badar, Brian Bell, Christian Zoellin, L. Sigal, B. Huott, James D. Warnock, Richard F. Rizzolo, Jesse Surprise, S. Carey, Frank Malgioglio, Arthur J. O'Neill, Guenter Mayer, Robert J. Sonnelitter, John Isakson, Dina Hamid, Michael G. Wood, Ricardo H. Nigaglioni, David Wolpert, Dureseti Chidambarrao |
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| Rok vydání: | 2018 |
| Předmět: |
Redundant array of independent memory
Random access memory Hardware_MEMORYSTRUCTURES Computer science business.industry 020208 electrical & electronic engineering 02 engineering and technology eDRAM 020202 computer hardware & architecture law.invention Microprocessor law Embedded system 0202 electrical engineering electronic engineering information engineering Cache Static random-access memory business Control bus Dram PCI Express |
| Zdroj: | ISSCC |
| Popis: | The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security [1] over the previous z13 system [2]. The system contains up to 24 central processor (CP) and 4 system controller (SC) chips. Each CP, shown in die photo A (Fig. 2.2.7), operates at 5.2GHz and is comprised of 10 cores, 2 PCIe Gen3 interfaces, an IO bus controller (GX), 128MB of L3 embedded DRAM (eDRAM) cache, X-BUS interfaces connecting to 2 other CP chips and one SC chip, and a redundant array of independent memory (RAIM) interface. Each core on the CP chip has 4MB of eDRAM L2 Data cache and 2MB of eDRAM L2 Instruction cache, with 128KB SRAM Instruction and 128KB SRAM Data L1 caches. Each SC, shown in die photo B (Fig. 2.2.7), operates at 2.6GHz and has 672MB of L4 eDRAM cache, X-BUS interfaces connecting to CP chips in the drawer and A-BUS interfaces connecting SCs on the other drawers. Both chips are 696mm2 and are designed in Global Foundries 14nm high performance (14HP) SOI FinFET technology with 17 layers of copper interconnect [3]. The CP contains 6.1B transistors, while the SC contains 9.7B transistors. The total IO bandwidth of the CP and SC are 2.9Tb/s and 5.5Tb/s, respectively. |
| Databáze: | OpenAIRE |
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