A 70 nm 16 Gb 16-Level-Cell NAND flash Memory
| Autor: | Mitsuaki Honma, S. Hoshi, Mark Murin, T. Shimizu, T. Kawaai, Michio Nakagawa, K. Nagaba, K. Kanebako, K. Kanazawa, Y. Komatsu, Arik Eyal, Hiroshi Maejima, K. Imamiya, H. Tabata, Menahem Lasser, K. Iwasa, T. Shano, M. Kosakai, Mark Shlick, Noboru Shibata, Masaki Fujiu, Hiroto Nakai, A. Inoue, Katsuaki Isobe, S. Yoshikawa, Avraham Meir, T. Takahashi, N. Motohashi |
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| Rok vydání: | 2008 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Multi-level cell CPU cache Computer science Nand flash memory business.industry NAND gate Parallel computing Flash memory Non-volatile memory Flash (photography) Logic gate Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Double data rate business Computer hardware |
| Zdroj: | IEEE Journal of Solid-State Circuits. 43:929-937 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more. |
| Databáze: | OpenAIRE |
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