Efficient test access mechanism optimization for system-on-chip
| Autor: | Krishnendu Chakrabarty, Vikram Iyengar, Erik Jan Marinissen |
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| Rok vydání: | 2003 |
| Předmět: |
Optimization problem
Computer science Heuristic (computer science) System testing Hardware_PERFORMANCEANDRELIABILITY Parallel computing Computer Graphics and Computer-Aided Design Reduction (complexity) Scalability Hardware_INTEGRATEDCIRCUITS Electronic design automation System on a chip Electrical and Electronic Engineering Integer programming Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:635-643 |
| ISSN: | 0278-0070 |
| Popis: | Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scalability for several industrial SOCs. Since the TAM optimization problem is NP-hard, recently proposed methods based on integer linear programming and exhaustive enumeration can be used to design limited test architectures with only a very small number of TAMs in a reasonable amount of time. In this paper, we explore a larger solution-space to design efficient test architectures with more TAMs. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to or lower than the testing times obtained using enumeration. Moreover, significant reduction can be obtained in the CPU time compared to enumeration. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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