| Autor: |
Sergio Camerlo, Lekhanh Dang, M. Hu, B. Ahmad, Yida Zou, S. Priore |
| Rok vydání: |
2004 |
| Předmět: |
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| Zdroj: |
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546). |
| DOI: |
10.1109/ectc.2004.1319067 |
| Popis: |
The development and deployment of very fast signaling technologies for communication across the backplane has introduced the need for a multidisciplinary design approach where the performance of the silicon to silicon communication channel is addressed from a variety of different perspectives. SerDes technology, connectors, vias, via stubs, and board materials are among the elements that need to be considered and modeled to reach-the desired trade off with respect to performance, cost and quality. In this study, component and system level electrical performance with back-drilled (or Counter Bored) Plated Through Holes is investigated, with simulation and testing examples. The methodology that is presented leverages multidisciplinary aspects of design and puts quality as a key ingredient of the development process. The results of this work and the associated methodology have been successfully shared across Business Units and Technology Groups. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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