High performance CMOS dual-modulus prescaler using selective latch technique

Autor:	Tae Geun Kim, Soo-Won Kim, Soon-Seob Lee, Se-Yeob Kim
Rok vydání:	2003
Předmět:	Engineering Dual-modulus prescaler business.industry Hardware_PERFORMANCEANDRELIABILITY Energy consumption Propagation delay Frequency divider CMOS Low-power electronics Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Radio frequency business
Zdroj:	ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
DOI:	10.1109/icvc.1999.820919
Popis:	This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 /spl mu/m CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b31e84d0c74ba0a7f2eb57ddafa2d63c https://doi.org/10.1109/icvc.1999.820919 Zobrazit plný text záznamu