A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation
| Autor: | Visvesh S. Sathe, Greg Taylor, Fahim ur Rahman |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Physics
Record locking Feedback control 020208 electrical & electronic engineering Phase (waves) Process (computing) Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Topology Temperature measurement Time–frequency analysis Phase-locked loop Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:2487-2500 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2019.2926191 |
| Popis: | This paper proposes computational locking (C-lock) in all-digital phase-locked loops (PLLs) to achieve rapid frequency and phase lock acquisition. The proposed approach employs a “lock-accelerator” module that accelerates lock-times ( $T_{\mathrm{ lock}}$ ) in both cold-start (PLL power-up) and re-lock scenarios without impacting steady-state PLL performance. The key premise underlying C-lock is that solving a system of accurate phase-frequency update equations at run-time provides superior lock performance compared to traditional PLLs that rely on linear feedback control. C-lock is readily amenable to runtime adaptation to Process, Voltage, and Temperature (PVT) variation. A 1–2 GHz computationally locked PLL was implemented in a 65-nm standard CMOS process. Measurements over 50 000 iterations of re-lock and cold-start experiments across multiple test-chips, supply-voltage ( $V_{\mathrm{ dd}}$ ), and operating temperatures indicate a mean re-lock time of 12 PLL reference clock cycles (12 $T_{\mathrm{ REFCLK}}$ ), and a “cold-start” $T_{\mathrm{ lock}}$ of 16 $T_{\mathrm{ REFCLK}}$ . Although the silicon demonstration of C-lock is based on a PLL designed for system clocking applications, the proposed approach is applicable to a broader class of PLLs. |
| Databáze: | OpenAIRE |
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