120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Autor:	Shin-Chi Lai, Ying-Hsi Lin, Jui Lung Chen, Ke-Horng Chen, Chao Chang Chiu, Chao Cheng Lee, Che Hao Meng, Hsiang An Yang, Tsung-Yen Tsai, Hsin Yu Luo, Chin-Long Wey, Chih-Wei Chang, Jian Ru Lin
Rok vydání:	2015
Předmět:	Engineering business.industry Clamper Electrical engineering Gate driver Electronic engineering Slew rate High voltage business Power (physics)
Zdroj:	ESSCIRC
DOI:	10.1109/esscirc.2015.7313884
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b295bdad8042ab6a5eed06efda9c0602 https://doi.org/10.1109/esscirc.2015.7313884 Zobrazit plný text záznamu