An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI

Autor:	Dennis M. Fischette, Richard J. Desantis, John Haeseon Lee
Rok vydání:	2009
Předmět:	Phase-locked loop Physics Synchronization (alternating current) Loop (topology) CMOS PLL multibit Hardware_INTEGRATEDCIRCUITS Electronic engineering Bandwidth (computing) Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Hardware_LOGICDESIGN Jitter
Zdroj:	CICC
DOI:	10.1109/cicc.2009.5280739
Popis:	An all-digital measurement circuit, built in 45-nm SOI-CMOS, enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circuit can be used to plot step-response vs. time, measure static phase error, and observe phase-lock status.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b2453c60bcaf9fcaa30c240d601ada06 https://doi.org/10.1109/cicc.2009.5280739 Zobrazit plný text záznamu