FIT
Autor: | F Y Young Evangeline, Wei Li, Bentian Jiang, Bei Yu, Peishan Tu, Xiaopeng Zhang, Ran Chen, Gengjie Chen |
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Rok vydání: | 2019 |
Předmět: |
Very-large-scale integration
Coupling Computer science Semiconductor device fabrication Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Timing closure Capacitance Signal 020202 computer hardware & architecture Chemical-mechanical planarization Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Simulation |
Zdroj: | DAC |
Popis: | Dummy fill insertion is a mandatory step in modern semiconductor manufacturing process to reduce dielectric thickness variation, and provide nearly uniform pattern density for the chemical mechanical planarization (CMP) process. However, with the continuous shrinking of the VLSI technology nodes, the coupling effects between the inserted metal fills and signal tracks can severely affect the original timing closure of the layout design. In this paper, we propose a robust, efficient and high-performance framework for timing-aware dummy fill insertion, which simultaneously minimizes the coupling capacitance of critical signal wires and other wires. The experimental results on IC/CAD 2018 contest benchmarks shows that our proposed framework outperforms contest winner by 8% on critical coupling capacitance with 3.3\times runtime speedup. |
Databáze: | OpenAIRE |
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