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This paper presents an Electronic Design Automation (EDA) methodology, capable of complete ASIC design flow. It reduces the Non-Recurring Engineering (NRE) Cost by introducing a novel concept of dynamic technology library (DTL), which stores the layout and physical design information of each block in a design. DTLs are dynamically updated with a verified physical block, whenever a new design (not available in DTL) is synthesized. The key feature of DTL is that it offers reusability of verified physical blocks at different levels of abstraction (registers, functional units, gates etc.) thereby reducing the NRE cost. A depth based search technique is employed that allows partial or full reuse of pre-compiled and optimized design layouts. The proposed tool flow is validated using 16 designs from IWLS2005 benchmark suite, including one 32-bit ALU and a 15 tap FIR filter (widely used as a signal processing element). It is shown that the reusability offered by DTL makes it possible to reduce the design time by more than 90% in comparison to other EDA methodologies. |
