3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture
| Autor: | Niccolo Righetti, Chandru Venkatasubramanian, Yifen Liu, Mebrahtu Henok T, Huang Guangyu, Haitao Liu, Xiangyu Yang, Salil Mujumdar, Akira Goda, Hiroyuki Sanda, Andrew Bicksler, Yu Yuwen, Srivardhan Gowda, Elisa Camozzi, Kevin L. Beaman, Tecla Ghilardi, Christian Caillat, Matt Ulrich, Randy J. Koval, Duo Mao |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES business.industry Computer science Electrical engineering Biasing 02 engineering and technology 021001 nanoscience & nanotechnology Transient analysis 01 natural sciences Flash (photography) Reliability (semiconductor) CMOS Logic gate 0103 physical sciences Electronic engineering Optimization methods 0210 nano-technology business |
| Zdroj: | 2017 IEEE International Memory Workshop (IMW). |
| Popis: | The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main features of GIDL-assisted body biasing and GIDL optimization methods ensuring the best erase effectiveness and variability control. Finally, the excellent reliability of the selector gate devices over Program/Erase cycles is demonstrated, proving the reliability of this technique. |
| Databáze: | OpenAIRE |
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