| Autor: |
Chan-Kyong Kim, Chang-Hyun Kim, Jung-Hwan Choi, Woo-Seop Kim, Sung-Woo Shin, Hwa-Yong Kim, Jae-Kwan Kim, Soo-In Cho |
| Rok vydání: |
2004 |
| Předmět: |
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| Zdroj: |
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519). |
| DOI: |
10.1109/isscc.2004.1332770 |
| Popis: |
A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 /spl mu/m DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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