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Conventional IC packaging requires device chips or dice to be packaged at the same level in a way we generally imagined, while newly developed and thriving 3D IC packaging utilizes skyscraper concept to stack numerous types of device chips with different functions occupying the exact same or similar footprint. This approach not only reduces overall package dimension and thickness, but also improves electronic interconnection performance, as well as provides other advantages like lower power dissipation and greater signal bandwidth. Nevertheless, because of the fact that there were tremendous amounts of money and integration efforts spent on fabrication process development, another variant of 3D IC packaging had started to emerge and rapidly flourished in recent years, and it's been referred to as a hybrid between 2D IC and 3D IC packaging, or more specifically, 2.5D IC packaging. Compared with 3D IC, 2.5D IC possesses the benefits of easier process configuration and lower production cost while maintains similar electrical performance as well as reduces certain obstacles where 3D IC packaging is prone to generate. In this paper, our current development of 2.5D IC packaging was demonstrated and displayed, followed by further elaboration of detailed process flow, including device wafer and interposer wafer fabrication in bumping part of process, intermediate die sawing process, and final die level assembly part of process. During the development stage, there were many challenges we had encountered, such as thin wafer handling, carrier bonding and debonding uniformity, warpage alleviation, material stress control, film delamination, as well as other lesser issues. We have offered and proposed certain approaches to particular challenges and the explanation of these challenges as well as proposed solutions was addressed in this paper to properly demonstrate the progression of our 2.5D IC packaging. |
