Carry select and input select adder for late arriving data

Autor:	C. Krygowski, E.M. Schwarz, T. McPherson
Rok vydání:	2002
Předmět:	Adder Logic synthesis Computer science Computation Carry (arithmetic) Serial binary adder Parallel computing Carry-save adder Hardware_ARITHMETICANDLOGICSTRUCTURES Integrated circuit layout
Zdroj:	Conference Record of The Thirtieth Asilomar Conference on Signals, Systems and Computers.
DOI:	10.1109/acssc.1996.600853
Popis:	An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b0c404fa0b7a1ae163f1d28adbd002db https://doi.org/10.1109/acssc.1996.600853 Zobrazit plný text záznamu