| Popis: |
modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time.The design and simulation work for 6T-SRAM, NC-SRAM, Asymmetric SRAM, PP-SRAM, and P3-SRAM topologies have been carried out to see their power consumption and performance at 45nm CMOS technology at 300 o K for VDD=0.7V and 0.8V. At VDD=0.8V, P3-SRAM consumes 69.069%, 13.61%, 82.03% and 86.11% less standby power than 6T-SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively.Similarly, the dynamic power consumed by P3- SRAM is 88.88%, 89.23%, 85.25% and 89.5% less than 6T- SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively at VDD=0.8V. |
