Hyper switching memory utilization on hybrid main memory for improved task execution and reduced power consumption
| Autor: | M. Prabhu, R. Vijay, Har Narayan Upadhyay |
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| Rok vydání: | 2020 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Computer Networks and Communications Computer science 020208 electrical & electronic engineering Process (computing) 02 engineering and technology 020202 computer hardware & architecture Reliability engineering Power (physics) Reduction (complexity) Task (computing) Artificial Intelligence Hardware and Architecture Power consumption 0202 electrical engineering electronic engineering information engineering Software Dram |
| Zdroj: | Microprocessors and Microsystems. 72:102891 |
| ISSN: | 0141-9331 |
| DOI: | 10.1016/j.micpro.2019.102891 |
| Popis: | The problem of lifetime maximization of PCM has been well studied. The arrival of non-volatile memory devices has replaced the traditional DRAM. Still the DRAM has many limitations on endurance and high power write operations. Similarly, number of designs has been discussed earlier to maximize the lifetime of PCM by catching the main memory at available DRAM. Still they could not achieve the performance on power consumption reduction and increasing memory utilization. To improve the performance in power consumption reduction and lifetime maximization, and categorical model is presented in this paper. The proposed method categorizes the processes according to their memory access activity. The categorized process has been allocated to respective part of hybrid memory which encourages maximum read and minimum write in PCM. The proposed method increases the lifetime of PCM than other methods. |
| Databáze: | OpenAIRE |
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