A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor
Autor: | Vijay Kiran Kalyanam, Eric Mahurin, Keith Bowman, Jacob A. Abraham |
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Rok vydání: | 2020 |
Předmět: | |
Zdroj: | VLSI Circuits |
Popis: | A proactive clock-gating system (PCGS) in a 7nm Qualcomm¯ Hexagon™ digital signal processor (DSP) predicts supply voltage (V DD ) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F CLK ) to reduce the V DD droop. Silicon measurements demonstrate 10% higher F CLK or 5% lower V DD . |
Databáze: | OpenAIRE |
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